View IDT74LVCH32501A_283352.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IDT74LVCH32501A 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 36-BIT REGISTERED TRANSCEIVER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD
* Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * CMOS power levels (0.4 W typ. static) * All inputs, outputs, and I/O are 5V tolerant * Supports hot insertion * Available in 114-ball LFBGA package
IDT74LVCH32501A
FEATURES:
DESCRIPTION:
DRIVE FEATURES: APPLICATIONS:
* High Output Drivers: 24mA * Reduced system switching noise
* 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems
This 36-bit registered transceiver is built using advanced dual metal CMOS technology. This device combines D-type latches and D-type flipflops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For Ato-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flipflop on the LOW-to-HIGH transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B port to A port is similar but requires using OEBA, LEBA and CLKBA. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The LVCH32501A has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The LVCH32501A has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
B3 1OEAB J4 1CLKBA K3 1LEBA J3 1OEBA 1CLKAB 1LEAB A4 A3 C A2 1A1 D C D A5 1B1
2OEAB 2CLKBA 2LEBA 2OEBA 2CLKAB 2LEAB
L3 V4 W3 V3 K5 K2 C D C D L5 2B1
L2 2A1
C D
C D
C D
C D
TO 17 OTHER CHANNELS
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
(c)2000 Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-4910/1
IDT74LVCH32501A 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
6
1B2
1B4
1B6
1B8
1B10
1B12
1B14
1B15
1B17
NC
2B2
2B4
2B6
2B8
2B10
2B12
2B14
2B15
2B17
5
1B1
1B3
1B5
1B7
1B9
1B11
1B13
1B16
1B18
2CLKAB
2B1
2B3
2B5
2B7
2B9
2B11
2B13
2B16
2B18
4 1CLKAB
GND
GND GND
VCC VCC
1A7
GND GND
GND GND
1A11
VCC VCC
GND 1CLKBA GND GND
1A16
GND
GND GND
VCC VCC
2A5
GND GND
GND GND
2A9
VCC VCC
GND 2CLKBA GND
3
1LEAB 1OEAB
1OEBA 1LEBA 2OEAB
GND
2A13
2OEBA 2LEBA
2
1A1
1A3
1A5
1A9
1A13
1A18
2LEAB
2A1
2A3
2A7
2A11
2A16
2A18
1
1A2 A
1A4 B
1A6 C
1A8 D
1A10 E
1A12 F
1A14 G
1A15 H
1A17 J
NC
K
2A2 L
2A4 M
2A6 N
2A8 P
2A10 R
2A12 T
2A14 U
2A15 V
2A17 W
LFBGA TOP VIEW
114 BALL LFBGA PACKAGE ATTRIBUTES
1.5mm Max. 1.4mm Nom. 1.3mm Min.
0.8mm
6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W
TOP VIEW
A 1 2 3
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
5.5mm 4 5 6
16mm
2
IDT74LVCH32501A 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM TSTG IOUT IIK IOK ICC ISS Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND -0.5 to +6.5 -65 to +150 -50 to +50 -50 100
Unit V C mA mA mA
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 6.5 6.5 Max. 6 8 8 Unit pF pF pF
NOTE: 1. As applicable to the device type.
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Names OEAB OEBA LEAB LEBA CLKAB CLKBA Ax Bx Description A-to-B Output Enable Input B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs or B-to-A 3-State Outputs(1) B-to-A Data Inputs or A-to-B 3-State Outputs(1)
FUNCTION TABLE(1,2)
Inputs OEAB L H H H H H H LEAB X H H L L L L CLKAB X X X L H Ax X L H L H X X Outputs Bx Z L H L H B(3) B(4)
NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH Transition 2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 3. Output level before the indicated steady-state conditions were established. 4. Output level before the indicated steady-state conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. - 75 75 -- -- --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- 500
Unit A A A
3
IDT74LVCH32501A 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC -- -- -- -- -- -- -- -0.7 100 -- -- -- 50 -1.2 -- 10 10 500 A V mV A VCC = 3.6V VO = 0 to 5.5V -- -- 10 A Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VI = 0 to 5.5V Test Conditions Min. 1.7 2 -- -- -- Typ.(1) -- -- -- -- -- Max. -- -- 0.7 0.8 5 A V Unit V
Quiescent Power Supply Current Variation
3.6 VIN 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND
A
NOTES: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
4
IDT74LVCH32501A 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 25C
Symbol CPD CPD Parameter Power Dissipation Capacitance per Transceiver Outputs enabled Power Dissipation Capacitance per Transceiver Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tSU tH tW tW tSK(o) Parameter Propagation Delay Ax to Bx or Bx to Ax Propagation Delay LEBA to Ax, LEAB to Bx Propagation Delay CLKBA to Ax, CLKAB to Bx Output Enable Time OEBA to Ax, OEAB to Bx Output Disable Time OEBA to Ax, OEAB to Bx Set-up Time, HIGH or LOW Ax to CLKAB, Bx to CLKBA Hold Time, HIGH or LOW Ax to CLKAB, Bx to CLKBA Set-up Time HIGH or LOW Ax to LEAB,Bx to LEBA Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA LEAB or LEBA Pulse Width HIGH CLKAB or CLKBA Pulse Width HIGH or LOW Output Skew(2) 3 3 -- -- -- -- 3 3 -- -- -- 500 ns ns ps Clock LOW ClockHIGH 3 2 1.5 -- -- -- 3 2 1.5 -- -- -- ns ns 0 -- 0 -- ns 3 -- 3 -- ns 1.5 6.5 1.5 5.8 ns 1.5 6 1.5 5.6 ns 1.5 6 1.5 5.3 ns 1.5 6 1.5 5.3 ns Min. 1.5 Max. 5.2 VCC = 3.3V 0.3V Min. 1.5 Max. 4.6 Unit ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
5
IDT74LVCH32501A 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
VIH VT 0V VOH VT VOL VIH VT 0V
LVC Link
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 Pulse (1, 2) Generator VIN D.U.T. RT 500 CL
LVC Link
SAME PHASE INPUT TRANSITION
VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
VLOAD Open GND
tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
tPHL
6 2.7 1.5 300 300 50
tPHL
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
LVC Link
VOUT
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC Link
INPUT
tPLH1
tPHL1
VIH VT 0V VOH VT VOL VOH VT VOL
Set-up, Hold, and Release Times
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE VT
LVC Link
VT
OUTPUT 1
tSK (x)
tSK (x)
OUTPUT 2 tPLH2 tPHL2
Pulse Width
LVC Link
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
6
IDT74LVCH32501A 3.3V CMOS 36-BIT REGISTERED TRANSCEIVER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT LVC X XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package
BF 501A
Low-Profile Fine Pitch Ball Grid Array 36-bit Registered Transciever with 3-State Outputs
32 H 74
32-bit Bus Density, 24mA Bus-hold -40C to +85C
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
7

▲Up To Search▲

Price & Availability of IDT74LVCH32501A

	To Download IDT74LVCH32501A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .